Some integrated circuits include several similar circuit blocks that are arranged in the integrated circuit in close proximity to each other and to shared circuitry. Moreover, in some of these integrated circuits, several circuit blocks are activated substantially simultaneously, resulting in a condition referred to herein as localized supply noise. More specifically, this simultaneous activation of the circuit blocks can cause a relatively large localized change in the voltage level at the supply voltage buses in the areas near the activated circuit blocks. In this context, the term "supply noise" as used herein refers to both dips and rises in the localized voltage level. Supply noise in the supply voltage levels may cause circuitry in these regions to operate improperly or with degraded performance. Because supply noise from more than one circuit block may be additive, this problem is exacerbated in mirrored placement arrangements that are commonly used in some types of integrated circuit devices.
FIG. 1 is a diagram illustrative of a portion of conventional mirrored array block arrangement 10 for a memory device. Mirrored arrangements are typically used to allow the circuit blocks to share circuitry placed between the circuit blocks. For example, the shared circuitry may include control logic, address decoders, charge pumps, etc. In this portion of arrangement 10, shared circuitry 11 is disposed between array blocks 12.sub.1 -12.sub.4 and 13.sub.1 -13.sub.4. Array blocks 12.sub.1 -12.sub.4 and 13.sub.1 -13.sub.4 are arranged in mirrored-symmetry about shared circuitry 11 in a line that contains the array blocks and shared circuitry. In particular, array blocks 12.sub.4 and 13.sub.1 are located closest to and on opposite sides of shared circuitry 11, with array blocks 12.sub.3 and 13.sub.2 being next closest to and on opposite sides of shared circuitry 11, and so on.
In addition, in this example of a conventional system, the activation of the array blocks is mirrored. More specifically, when address location 00X (for an N-bit address, X indicates the least significant N-2 bits of the address) is being accessed, the two array blocks located closest on either side of shared circuitry 11 (i.e., array blocks 12.sub.4 and 13.sub.1) are activated, as indicated by arrows A1 in FIG. 1. The address 00X represents an subset of the full address corresponding to the selection or activation of array blocks. Those skilled in the art of memory devices will appreciate that additional lower level address bits are included in the full address for selecting particular wordlines within an array block. These lower level bits of the full address are omitted for clarity. Similarly, the full address may include additional higher order bits for selecting other array blocks. That is, the portion of the structure shown in FIG. 1 is typically part of a larger memory structure, with more memory arrays.
As can be seen in FIG. 1, the physical locations of the "00X" array blocks are mirrored about the location of shared circuitry 11. Similarly, when address location 01X is being accessed, array blocks 12.sub.3 and 13.sub.2 (i.e., the next closest array blocks on either side of shared circuitry 11) are activated as indicated by arrows A2. Likewise, address locations 10X and 11X respectively correspond to array block pairs 12.sub.2 and 13.sub.3, and 12.sub.1 and 13.sub.4, as indicated by arrows A3 and A4.
In this example, each array block includes two banks of sense amplifiers 14, one bank each on opposite sides of the array block and parallel to the wordlines corresponding to the array block. Array blocks typically have a large number of wordlines (e.g., 256 wordlines in a sixteen Mb DRAM device). For purposes of this description, a single representative wordline for each array block is shown in FIG. 1, with these wordlines corresponding to the same lower order address bits. For example, array blocks 12.sub.1 -12.sub.4, respectively, have wordlines 15.sub.1 -15.sub.4 running through the respective array block. Similarly, array blocks 13.sub.1 -13.sub.4, respectively, have wordlines 16.sub.1 -16.sub.4 running through the respective array block. As stated above, wordlines 15.sub.1 -15.sub.4 and 16.sub.1 -16.sub.4 all correspond to the same set of lower order address bits.
An array block decoder 17 receives an address (e.g., 00X through 11X) and activates the appropriate array block to activate the appropriate wordline. As shown schematically in FIG. 1, decoder 17 is connected to a set of decoder lines. More specifically, in this example, decoder 17 drives a first decoder line having segments 18.sub.1 and 19.sub.1, a second decoder line having segments 18.sub.2 and 19.sub.2, a third decoder line having segments 18.sub.3 and 19.sub.3, and a fourth decoder line having segments 18.sub.4 and 19.sub.4. Although shown in separate segments in FIG. 1 separated by decoder 17, the segments of a decoder line may be continuous. Further, for clarity, only four decoder lines and eight array blocks are shown. As previously mentioned, a memory device would likely include a much larger number of such array blocks, wordlines and decoder lines.
This conventional activation arrangement is typically implemented so that a particular decoder line corresponds to a particular pair of array blocks that are arranged in a mirrored fashion about shared circuitry 11. Connection structures (e.g., contacts and vias) are used to interconnect the decoder line to wordline decoders of the corresponding wordlines. In the example arrangement of FIG. 1, decoder line segments 18.sub.1 and 19.sub.1, respectively, are connected to the wordline decoders D15.sub.4 and D16.sub.1 of wordlines 15.sub.4 and 16.sub.1 through connection points C0 and C0', respectively. Similarly, decoder line segments 18.sub.2 and 19.sub.2 are respectively connected to the wordline decoders D15.sub.3 and D16.sub.2 for wordlines 15.sub.3 and 16.sub.2 through connection structures C1 and C1', respectively, and so on.
One problem with this conventional mirrored arrangement is that when address location 00X is accessed, the two array blocks closest to shared circuitry 11 (i.e., array blocks 12.sub.4 and 13.sub.1) are activated. The activation of the array blocks and the associated sense amplifiers tend to cause localized supply noise. Moreover, due to the close proximity of shared circuitry 11 to the activated array blocks, the supply bus regions proximate to shared circuitry 11 experience relatively high localized supply noise, thereby making shared circuitry 11 more susceptible to erroneous operation and/or degraded performance when this particular address is accessed. Accordingly, there is a need for a method or structure that reduces the worst case supply bus noise for circuit block architectures that use shared circuitry with minimal impact on the circuit block/shared circuitry architecture.